philips semiconductors product specification n-channel trenchmos ? transistor PHX9NQ20T , phf9nq20t features symbol quick reference data ?trench? technology low on-state resistance v dss = 200 v fast switching low thermal resistance i d = 5.2 a r ds(on) 400 m ? general description n-channel, enhancement mode field-effect power transistor using trench technology, intended for use in off-line switched mode power supplies, t.v. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. the PHX9NQ20T is supplied in the sot186a (fpak) conventional leaded package pinning sot186a (fpak) sot186 (fpak) pin description 1 gate 2 drain 3 source case isolated limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v dss drain-source voltage t j = 25 ?c to 175?c - 200 v v dgr drain-gate voltage t j = 25 ?c to 175?c; r gs = 20 k ? - 200 v v gs gate-source voltage - 20 v i d continuous drain current t hs = 25 ?c; v gs = 10 v - 5.2 a t hs = 100 ?c; v gs = 10 v - 3.3 a i dm pulsed drain current t hs = 25 ?c - 21 a p d total power dissipation t hs = 25 ?c - 25 w t j , t stg operating junction and - 55 150 ?c storage temperature d g s 123 case 12 3 case november 2000 1 rev 1.100
philips semiconductors product specification n-channel trenchmos ? transistor PHX9NQ20T , phf9nq20t avalanche energy limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit e as non-repetitive avalanche unclamped inductive load, i as = 7.2a; - 93 mj energy t p = 100 s; t j prior to avalanche = 25?c; v dd 25 v; r gs = 50 ? ; v gs = 10 v; refer to fig;15 i as peak non-repetitive - 8.7 a avalanche current thermal resistances symbol parameter conditions min. typ. max. unit r th j-hs thermal resistance junction - - 5 k/w to mounting base r th j-a thermal resistance junction sot186a package, in free air - 55 - k/w to ambient electrical characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)dss drain-source breakdown v gs = 0 v; i d = 0.25 ma; 200 - - v voltage t j = -55?c 178 - - v v gs(to) gate threshold voltage v ds = v gs ; i d = 1 ma 2 3 4 v t j = 150?c 1 - - v t j = -55?c - 6 v r ds(on) drain-source on-state v gs = 10 v; i d = 4.5 a - 300 400 m ? resistance t j = 150?c - - 0.94 ? g fs forward transconductance v ds = 25 v; i d = 4.5 a 3.8 6 - s i gss gate source leakage current v gs = 10 v; v ds = 0 v - 10 100 na i dss zero gate voltage drain v ds = 200 v; v gs = 0 v - 0.05 10 a current t j = 150?c - - 500 a q g(tot) total gate charge i d = 9 a; v dd = 160 v; v gs = 10 v - 24 - nc q gs gate-source charge - 4 - nc q gd gate-drain (miller) charge - 12 - nc t d on turn-on delay time v dd = 100 v; r d = 10 ? ;-8-ns t r turn-on rise time v gs = 10 v; r g = 5.6 ? -19-ns t d off turn-off delay time resistive load - 25 - ns t f turn-off fall time - 15 - ns l d internal drain inductance measured from drain lead to centre of die - 4.5 - nh l s internal source inductance measured from source lead to source - 7.5 - nh bond pad c iss input capacitance v gs = 0 v; v ds = 25 v; f = 1 mhz - 959 - pf c oss output capacitance - 93 - pf c rss feedback capacitance - 54 - pf november 2000 2 rev 1.100
philips semiconductors product specification n-channel trenchmos ? transistor PHX9NQ20T , phf9nq20t reverse diode limiting values and characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit i s continuous source current - - 8.7 a (body diode) i sm pulsed source current (body - - 35 a diode) v sd diode forward voltage i f = 9 a; v gs = 0 v - 0.85 1.2 v t rr reverse recovery time i f = 9 a; -di f /dt = 100 a/ s; - 92 - ns q rr reverse recovery charge v gs = -10 v; v r = 25 v - 0.5 - c isolation limiting value & characteristic t hs = 25 ?c unless otherwise specified symbol parameter conditions min. typ. max. unit v isol r.m.s. isolation voltage from all sot186a package; f = 50-60 hz; - 2500 v three terminals to external sinusoidal waveform; r.h. 65%; heatsink clean and dustfree v isol repetitive peak voltage from all sot186 package; r.h. 65%; - 1500 v three terminals to external clean and dustfree heatsink c isol capacitance from pin 2 to f = 1 mhz - 10 - pf external heatsink november 2000 3 rev 1.100
philips semiconductors product specification n-channel trenchmos ? transistor PHX9NQ20T , phf9nq20t fig.1. normalised power dissipation. pd% = 100 ? p d /p d 25 ?c = f(t mb ) fig.2. normalised continuous drain current. id% = 100 ? i d /i d 25 ?c = f(t mb ); v gs 10 v fig.3. safe operating area i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.4. transient thermal impedance. z th j-mb = f(t); parameter d = t p /t fig.5. typical output characteristics, t j = 25 ?c . i d = f(v ds ) fig.6. typical on-state resistance, t j = 25 ?c . r ds(on) = f(i d ) 0 20 40 60 80 100 120 140 ths / c pd% normalised power derating 120 110 100 90 80 70 60 50 40 30 20 10 0 with heatsink compound 0.01 0.1 1 10 1e-06 1e-05 1e-04 1e-03 1e-02 1e-01 1e+00 1e+01 pulse width, tp (s) transient thermal impedance, zth j-a (k/w) single pulse d = 0.5 0.2 0.1 0.05 0.02 0 20 40 60 80 100 120 140 ths / c id% normalised current derating 120 110 100 90 80 70 60 50 40 30 20 10 0 with heatsink compound 0 1 2 3 4 5 6 7 8 9 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 drain-source voltage, vds (v) drain current, id (a) 5 v tj = 25 c vgs = 10v 5.5 v 6 v 8 v 4.5 v 0.1 1 10 100 1 10 100 1000 drain-source voltage, vds (v) peak pulsed drain current, idm (a) d.c. 100 ms 10 ms rds(on) = vds/ id 1 ms tp = 10 us 100us 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 012345678910 drain current, id (a) drain-source on resistance, rds(on) (ohms) vgs = 10v tj = 25 c 8 v 5 v 6 v 5.5 v 4.5 v november 2000 4 rev 1.100
philips semiconductors product specification n-channel trenchmos ? transistor PHX9NQ20T , phf9nq20t fig.7. typical transfer characteristics. i d = f(v gs ) fig.8. typical transconductance, t j = 25 ?c . g fs = f(i d ) fig.9. normalised drain-source on-state resistance. r ds(on) /r ds(on)25 ?c = f(t j ) fig.10. gate threshold voltage. v gs(to) = f(t j ); conditions: i d = 1 ma; v ds = v gs fig.11. sub-threshold drain current. i d = f(v gs) ; conditions: t j = 25 ?c fig.12. typical capacitances, c iss , c oss , c rss . c = f(v ds ); conditions: v gs = 0 v; f = 1 mhz 0 1 2 3 4 5 6 7 8 9 10 0123456 gate-source voltage, vgs (v) drain current, id (a) tj = 25 c 150 c threshold voltage, vgs(to) (v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 junction temperature, tj (c) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 012345678910 id / (a) transconductance, gfs (s) tj = 25 c 150 c drain current, id (a) 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 gate-source voltage, vgs (v) minimum typical maximum normalised on-state resistance 0 0.5 1 1.5 2 2.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 junction temperature, tj c 10 100 1000 10000 0.1 1 10 100 drain-source voltage, vds (v) capacitances, ciss, coss, crss (pf) ciss coss crss november 2000 5 rev 1.100
philips semiconductors product specification n-channel trenchmos ? transistor PHX9NQ20T , phf9nq20t fig.13. typical turn-on gate-charge characteristics. v gs = f(q g ) fig.14. typical reverse diode current. i f = f(v sds ); conditions: v gs = 0 v; parameter t j fig.15. maximum permissible non-repetitive avalanche current (i as ) versus avalanche time (t av ); unclamped inductive load 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 5 10 15 20 25 30 35 gate charge, qg (nc) gate-source voltage, vgs (v) id = 9 a tj = 25 c vdd = 40 v vdd = 160 v 0.1 1 10 0.001 0.01 0.1 1 10 avalanche time, t av (ms) maximum avalanche current, i as (a) tj prior to avalanche = 150 c 25 c 0 1 2 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 source-drain voltage, vsds (v) source-drain diode current, if (a) tj = 25 c 150 c vgs = 0 v november 2000 6 rev 1.100
philips semiconductors product specification n-channel trenchmos ? transistor PHX9NQ20T , phf9nq20t mechanical data dimensions in mm net mass: 2 g fig.16. sot186a; the seating plane is electrically isolated from all terminals. notes 1. observe the general handling precautions for electrostatic-discharge sensitive devices (esds) to prevent damage to mos gate oxide. 2. refer to mounting instructions for f-pack envelopes. 3. epoxy meets ul94 v0 at 1/8". references outline version european projection issue date iec jedec eiaj sot186a to-220 0 5 10 mm scale plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead to-220 sot186a a a 1 q c k j notes 1. terminal dimensions within this zone are uncontrolled. terminals in this zone are not tinned. 2. both recesses are ? 2.5 0.8 max. depth d d 1 l l 2 l 1 b 1 b 2 e 1 e b w m 1 23 q e p t unit d b 1 d 1 e q q p l c l 2 (1) max. e 1 a 5.08 3 mm 4.6 4.0 a 1 2.9 2.5 b 0.9 0.7 1.1 0.9 b 2 1.4 1.2 0.7 0.4 15.8 15.2 6.5 6.3 e 10.3 9.7 2.54 14.4 13.5 t (2) 2.5 0.4 l 1 3.30 2.79 j 2.7 2.3 k 0.6 0.4 2.6 2.3 3.0 2.6 w 3.2 3.0 dimensions (mm are the original dimensions) 97-06-11 november 2000 7 rev 1.100
philips semiconductors product specification n-channel trenchmos ? transistor PHX9NQ20T , phf9nq20t mechanical data dimensions in mm net mass: 2 g fig.17. sot186; the seating plane is electrically isolated from all terminals. notes 1. observe the general handling precautions for electrostatic-discharge sensitive devices (esds) to prevent damage to mos gate oxide. 2. refer to mounting instructions for f-pack envelopes. 3. epoxy meets ul94 v0 at 1/8". references outline version european projection issue date iec jedec eiaj sot186 to-220 0 5 10 mm scale plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead to-220 exposed tabs sot186 a a 1 q c note 1. terminal dimensions within this zone are uncontrolled. terminals in this zone are not tinned. d d 1 l l 2 l 1 m q e 1 e b w m 1 23 e 1 e p b 1 unit d b 1 d 1 e q q p l c l 2 e 1 a 5.08 mm 4.4 4.0 a 1 2.9 2.5 b 0.9 0.7 1.5 1.3 0.55 0.38 17.0 16.4 7.9 7.5 e 10.2 9.6 5.7 5.3 e 1 2.54 14.3 13.5 10 0.4 l 1 (1) 4.8 4.0 1.4 1.2 4.4 4.0 w 3.2 3.0 m 0.9 0.5 dimensions (mm are the original dimensions) 97-06-11 november 2000 8 rev 1.100
philips semiconductors product specification n-channel trenchmos ? transistor PHX9NQ20T , phf9nq20t definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. ? philips electronics n.v. 2000 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. november 2000 9 rev 1.100
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